Silicon IPs Library: Standard Cells

Catalog of Standard Cells Library from:

Perf.
optimiz.
volt.
range
Supported
processes
DOWNLOAD
65 nm
eLLvHD
Low Leakage
High Density
1.08 V
1.32 V
TSMC LP
SMIC

eLCvHS

Low Dynamic Power
High Speed

1.08 V
1.32 V
TSMC LP
SMIC
eVSvHD
Voltage Scaling
High Density
0.7 V
1.32 V
TSMC LP
SMIC
90 nm
eLLvHD
Low Leakage
High Density
1.08 V
1.32 V
TSMC LP
SMIC

eLCvHS

Low Dynamic Power
High Speed
0.9 V
1.1 V
TSMC GP
TSMC LP
eVSvHD
Voltage Scaling
High Density
0.7 V
1.32 V
TSMC LP
SMIC
uHVuLL
High Voltage
Low Leakage
1.6 V
3.6 V
TSMC GP
TSMC LP
SMIC LP
0.13 μm
eLLvHD
Low Leakage
High Density
1.08 V
1.32 V
TSMC LP
SMIC
eLCvHS
Low Dynamic Power
High Speed
1.08 V
1.32 V
TSMC GP
SMIC GP
eVSvHD
Voltage Scaling
High Density
0.7 V
1.32 V
TSMC GP
SMIC
uHVuLL
High Voltage
Low Leakage
1.6 V
3.6 V
TSMC GP
TSMC LP
SMIC LP
0.18 μm
uHDvLC
High Density
Low Dynamic Power
1.6 V
2.0 V
TSMC
SMIC
eLLvHD
Low Leakage
High Density
1.6 V
2.0 V
TSMC
SMIC
eLCvHS
Low Dynamic Power
High Speed
1.6 V
2.0 V
TSMC
SMIC
eVSvHD
Voltage Scaling
High Density
0.9 V
2.0 V
TSMC
SMIC
uHVuLL
High Voltage
Low Leakage
1.6 V
3.6 V
TSMC
SMIC
0.25 μm
eVSvLL
Voltage Scaling
Low Leakage
1.6 V
2.75 V
TSMC
SMIC
eLCvHS
High Density
Low dynamic power
2.25 V
2.75 V
TSMC
SMIC
eVSvHD
Voltage scaling
Low dynamic power
1.2 V
2.75 V
TSMC
SMIC
uHVuLL
High Voltage
Low Leakage
2.25 V
3.6 V
TSMC
SMIC
eRHeLC
Radiation hardened
Low dynamic power
2.25 V
2.75 V
IHP
 

 

* STEM : sub-library ultimately optimized for one criterion while preserving a high performance on a second criterion.

A panel of Front-ends for an easy evaluation of our standard cells libraries:

SEDUCTION* Front-end:

Presentation sheet

 

CHARM* Front-end:

  • Charm “Try and Buy”  evaluation tutorial
  • ViC Specification including the performances for one representative corner of the stem
  • Library view for Synopsys incl. Capacity Load- with 1 WLM; with the corner defined above; .lib contains area, timing and power consumption for the mentioned corner
  • Verilog-HDL/VHDL simulation models

 

DESIGN-IN* Front-end:

CHARM front-end but with all the corners for the STEM

 

INTEGRATION* Front-end:

  • Integration “Try and Buy” evaluation tutorial
  • DESIGN-IN evaluator
  • Abstract file compatible - incl. obstructions blocks => lef file DRC clean
  • Antenna file
  • Header LEF file