Silicon IPs Library: Embedded ROMs

Catalog of Low-Power, High density, and low-voltage from:

Product name
Perf.
optimiz.
volt.
range
Supported
processes
DOWNLOAD
65 nm
tROMet-HD-PHOENIX
Ultra Low Leakage
Ultra High Density
1.08 V
1.32 V
TSMC LP
sROMet-LL-PHOENIX
Ultra Low Leakage
High Density
Low Power
1.08 V
1.32 V
TSMC LP

sROMet-LP-CASSIOPEIA-HSL

Low Power
Low Leakage
High Density
1.08 V
1.32 V
TSMC LP
STM LP
90 nm

sROMet-LL-PHOENIX

Ultra Low Leakage
High Density
Low Power
1.08 V
1.32 V
TSMC LP
-
-
tROMet-HD-PHOENIX
Ultra High Density
Ultra Low Leakage
1.08 V
1.32 V
TSMC LP
0.13 μm
sROMet-LP-CASSIOPEIA-HSL
Low Power
Voltage Scaling
High Density
1.1 V
1.7 V
TSMC LP
-
tROMet-LP-CASSIOPEIA
Ultra High Density
Low Power
1.2 V
1.65 V
TSMC LP
TSMC GP
sROMet-LL-PHOENIX
Ultra Low Leakage
High Density
Low Power
1.08 V
1.32 V
TSMC GP
sROMet -uLLeVS PHOENIX
Low Leakage
Voltage Scaling
0.7 V
1.32 V
TSMC GP
0.18 μm
dROMet-LP-CASSIOPEIA -SD
Ultra Low Leakage
Low Power
High Density
1.62 V
1.98 V
TSMC GP
-
SMIC
-
UMC
CSM
SIL
-
1st Silicon
Dongbu-Anam
dROMet-LP-CASSIOPEIA -VS
Ultra Low Leakage
Low Power
High Density
Voltage Scaling
1.0 V
1.98 V
TSMC GP
-
SMIC
-
UMC
-
CSM
-
SIL
1st Silicon
Dongbu-Anam
tROMet-LP-CASSIOPEIA
Ultra High Density
Low Power
Voltage Scaling
1.45 V
1.98 V
TSMC GP
-
dROMet-UHD-CASSIOPEIA-HSL
Ultra High Density
Low Power
Voltage Scaling
1.45 V
1.98 V
TSMC GP
0.25 μm
dROMet-LP_ CASSIOPEIA
High Density
Low Power
Voltage Scaling
1.5 V
2.75 V
TSMC

-
UMC
-
CSM
0.35 μm
dROMet-LP-CASSIOPEIA
High Density
Low Power
Voltage Scaling
2.3 V
3.6 V
TSMC
sROMet-ULP-CASSIOPEIA-HSL
Ultra Low Power
High Density
Voltage Scaling
1.2 V
3.6 V
Specific process
-
-
diROM-HS-PEGASUS
High Density
High Speed
3.0 V
3.6 V
TSMC
-

 

SEDUCTION* Front-end: Our memories seduce through their key performances and functionalities introduced in a presentation sheet (PS)

CHARM* Front-end: Enables to choose the right architecture depending on the application requirements. Datasheet, preliminary performances and benchmarks available. Online Front-end generator available for a selection of instances.

DESIGN-IN* Front-end: Soc integrators are provided with VHDL/Verilog simulation models, .lib with timing & power consumption in typical case conditions @ nominal voltage + Benchmarks. Online Front-end generator available for all instances in the flexibility of the generator.

INTEGRATION* Front-end: ViC Specification, .lib for 3 to 5 corners according to voltage range, .dB, .lef, LVS sockets + Benchmarks. Online Front-end generator available for all instances in the flexibility of the generator, including abstract file for the safest integration into the SoC.