SMASH Overview

SMASH is a true Analog-Mixed Signal, Multi-language, Multi-level Simulator

Identically available on:

Windows 2000/XP

Sun Solaris 7 or higher

Redhat Linux 7.3 to 9 and RHEL4

 

 

 

Are you experiencing these challenges in your IC design?

1) Unable to easily perform mixed-signal simulation?

Solution

SMASH allows greater flexibility for partitioning your design at any level through Mixed-Signal Multi-Language simulation. It simulate any mix of SPICE, Verilog, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS, and C/SystemC design files. Learn More.

2) Design variability and debugging is not manageable at 65nm and below?

Solution

SMASH offers multiple innovative features to win the war against design failure:

  a. Validate design robustness with respect to statistical parameter variation
  b. Automatic detection of Multiple Operating Points to ensure design operation for all bias points
  c. Sensitivity Locate to identify the contribution of each device to on-chip dispersion
  d. Imbalance Locate to diagnose design yield losses due to process dispersion
  e. High Impedance Nets detection to avoid mal-functioning circuits, yield losses, excessive leakage power ..etc
  Learn More

3) Harmonic Balance Simulation generates inaccurate noise results for your non-linear circuits (Examples: sample and hold circuits, Switched-C filters, Oscillators (VCO), Freq dividers & multipliers, Charge Pumps, PLL)

Solution

Use the transient noise capability of SMASH that allows you to simulate accurate noise results in the time domain.

4) Unable to simulate different types of Jitter?

Solution

Simulating the jitters themselves, as well as the impact of jitters on designs, is turned into a quick and fun task with SMASH. Learn More. SMASH enables the implementation of a unique methodology for accurate and fast simulation (400 times faster than traditional SPICE simulators) for all types of jitter: Long-term jitter, cycle-to-cycle jitter and cycle jitter. See Tutorial

5) Analyzing the waveform graphically only doesn't help you catch serious design problems such as: gate oxide breakdown, excessive heating, source or drain to bulk junction breakdown and many other?

Solution

SMASH uses dynamic ERC analysis to perform Electrical Rule Checks (ERC) and Safe Operating Area (SOA) checks in order to control that circuit variables (currents, voltages, powers, threshold and saturation voltages, internal variables,...) stay inside a given interval or do not exceed predefined limits. Static analysis can provide power consumption estimations, check transistor ratios, detect short-circuits and isolated circuits, as well as check other specialized electrical rules. Learn More.

6) After completing your system validation using Matlab, you start the VHDL or Verilog coding from scratch with no link to your Matlab system design?

Solution

SMASH allows linking the system design and the circuit design through co-simulation between MatLab-Simulink and Verilog and/or VHDL (and soon Spice and VHDL-AMS). Learn More.